Today, the vast majority of memory used by desktops, notebooks, and mobile devices is unbuffered non-ECC (Error Checking and Correction) DRAM. In fact, unless one is running an Intel or AMD CPU that can support ECC memory unbuffered ECC DRAM is the only choice for most users. Intel Xeons, for example, support ECC memory, while even the new Core i7′s do not. AMD has much broader ECC support at the CPU level, but many AMD motherboards do not support ECC memory features so it is not universal.
ECC MEMORY WHAT IT DOES
Error Checking and Correction (ECC) memory is mostly considered essential in enterprise environments these days. Single bit error checking and correction within an 8-bit byte allows for single bit errors to be both detected and corrected when they occur. Interestingly enough, the way this single bit ECC works is not all that unlike RAID 4 and RAID 5 where an XOR algorithm is used to generate parity bits. Instead of losing usable memory capacity, memory makers tend to add an additional chip to ECC memory for every eight storage chips. When a single bit error is detected, the parity information is used to reconstruct the data with an error. Again, this is conceptually similar to how RAID 4 and RAID 5 can scrub and fix data errors in storage arrays. Larger errors than multi-bit can be detected but not corrected by the single bit ECC type of parity scheme.
For desktops, this is less important as a lot of figures put single-bit errors in the range of 1 per 1GB or 1 per 2GB of memory each month. To a desktop user, this may cause a program to crash, or at worst require a reboot. In servers, ECC is essential to maintaining both data integrity and uptime. With the current minor cost differential of ECC versus non-ECC unbuffered DIMMs, there is little reason to get non-ECC memory for a server.
UNBUFFERED ECC VERSUS REGISTERED ECC MEMORY
Adding to the ECC concept, there are two concepts at play, unbuffered and registered ECC memory modules. The basic difference is that memory commands in unbuffered memory configurations go directly from the controller to the memory module, while in registered memory configurations the commands are sent first to the memory banks’ registers prior to being sent to the modules. This concept may sound difficult, but here is the very simple/ conceptual view regarding what is going on.
In the above example the memory controller accesses the memory banks directly. The above assumes that the memory controller resides within the CPU package as it does in modern CPU architectures. Looking at older systems, the memory controller resided within the CPU northbridge. Compare this to the registered memory example below.
Here the CPU communicates with the registers for the banks of memory on each module. From there, these registers communicate with the DRAM. The implications of this are twofold. First, on a negative side, instructions take approximately one CPU cycle longer due to the intermediary of the bank register. On the positive side, this buffering reduces the strain on the CPU’s memory controller because it points to the dedicated intermediary register versus accessing the DRAM directly. It is easier on the memory controller to deal with a fewer number of targets.
This feature is very important in server scenarios because, for example, an Intel 3400 series platform, such as the Supermicro X8SI6-F or Intel S3420GPLC supports 16GB unbuffered ECC and 32GB registered ECC memory. Likewise, in dual processor systems, such as the E5600 series based Supermicro X8DTH-6F recently reviewed on ServeTheHome, the delta is much greater with up to 48GB of unregistered ECC or 192GB of registered ECC memory. For virtualization environments where memory, and memory bandwidth is key to achieving high consolidation and density metrics, Registered ECC memory is generally the way to go. If one purchases a server with unregistered ECC DIMMs, then requires additional capacity, then the upgrade operation will require a pull and replace all UDIMM modules making it an expensive proposition.
In this article hopefully one can get a conceptual view of the difference between the unbuffered ECC memory and registered ECC memory to help inform selection decisions.